Skip to main content

Semiconductor PN Junction Depletion Width Calculator

When P-type and N-type semiconductors are brought into metallurgical contact, mobile carriers diffuse across the junction, leaving behind uncompensated ionized dopant atoms that form a space-charge depletion region.

Acceptor impurity concentration in P-region.

Donor impurity concentration in N-region.

Dielectric constant of semiconductor (11.7 for Silicon, 12.9 for GaAs).

Lattice temperature (300 K room temp).

External reverse bias voltage applied to cathode.

Calculated Result
0.327 µm

Total Depletion Layer Width (W)

Built-in Potential (V_bi)

0.753 V

P-side Width (x_p)

0.298 µm

N-side Width (x_n)

0.030 µm

Peak Junction Electric Field (E_max)

46.0 kV/cm

Calculation Breakdown

  1. V_bi = V_t · ln(N_A·N_D / n_i²)0.753 V
  2. W = √[ (2ε/q) · (N_A+N_D)/(N_A·N_D) · (V_bi + V_R) ]0.327 µm
  3. E_max = 2·V_total / W46.0 kV/cm

What Is the Semiconductor PN Junction Depletion Width Calculator?

The depletion region is an insulating zone depleted of free mobile charge carriers in a semiconductor PN junction.

It creates an internal electrostatic potential barrier that blocks majority carrier diffusion in equilibrium.

How Does the Semiconductor PN Junction Depletion Width Calculator Work?

Calculates thermal voltage Vt = kb * T / q and built-in potential Vbi.

Solves Poisson's equation to find total depletion width W.

Applies charge neutrality to partition width between P-side and N-side.

Evaluates peak triangular electric field at the metallurgical interface.

Semiconductor PN Junction Depletion Width Calculator Formula & Variables

The core mathematical equation utilized by this calculator is expressed as:

V_{bi} = V_t \ln\left( \frac{N_A N_D}{n_i^2} \right), \quad W = \sqrt{ \frac{2 \epsilon_s}{q} \left(\frac{N_A + N_D}{N_A N_D}\right) (V_{bi} + V_R) }, \quad E_{max} = \frac{2 (V_{bi} + V_R)}{W}

Poisson depletion approximation for step-junction semiconductor diode electrostatics.

How to Use the Semiconductor PN Junction Depletion Width Calculator

  1. Enter P-side acceptor (NA) and N-side donor (ND) concentrations in cm^-3.
  2. Specify semiconductor permittivity and operating temperature.
  3. Enter applied reverse bias voltage (0 for zero-bias equilibrium).

Step-by-Step Example Calculation

Silicon Step-Junction Diode at Zero Bias

Input Values:

acceptorDopingNaCm3:10000000000000000
donorDopingNdCm3:100000000000000000
relativePermittivityEr:11.7
temperatureKelvin:300
reverseBiasVoltageV:0
Worked Steps: Equilibrium space-charge profile in standard planar silicon diode.

Understanding Your Result

The depletion region penetrates predominantly into the lightly doped side of asymmetric junctions (e.g. p+ n).

Reverse bias widens the depletion layer, increasing breakdown voltage and decreasing junction capacitance.

Factors That Affect the Result

  • Doping concentration: Higher doping shrinks depletion width and increases junction capacitance and peak field.
  • Temperature: Higher temperature increases intrinsic carrier concentration ni, lowering built-in potential Vbi.

When Should You Use This Calculator?

  • Designing junction field-effect transistors (JFET), PIN photodetectors, and solar cells.
  • Calculating junction capacitance (C_j = eps / W) for high-frequency RF diodes.

Assumptions & Limitations

  • Assumes abrupt step-junction doping profile under full depletion approximation.
  • Assumes room temperature non-degenerate doping regimes.

Frequently Asked Questions

Calculation Accuracy & Reference Note

Standard semiconductor physics equation validated by Sze & Ng.

Explore more tools and calculators in Physics Calculators